A continuing and ongoing trend in the semiconductor field is the ever-increasing density of circuit components in integrated circuits. More and more circuit components are being designed within a given integrated circuit area. Thus, techniques have been developed to substantially reduce the sizes of active devices, metal lines, and inter layer dielectrics, among other components.
With the reduction of circuit component sizes comes a host of problems due to the closer proximity of circuit components. One such problem is cross-talk or electromagnetic interference between adjacent circuit components. For example, a signal present on a metallization line may interfere with another signal present on an adjacent metallization line. Another problem associated with the close proximity of circuit components is the potential increased signal delay and reduction in frequency bandwidth. That is, the presence of a grounded metallization layer in proximity to a metallization layer carrying a signal may decrease the signal propagation speed leading to possible delay errors. Also, a close proximity grounded layer may reduce the frequency bandwidth of the signal on an adjacent metallization line. These problems stem from the capacitive coupling between adjacent circuit components.
The capacitive coupling between adjacent circuit components is proportional to the relative dielectric constant of the material separating the circuit components and inversely proportional to the distance separating the circuit components. Thus, in order to reduce the capacitive coupling between the adjacent circuit components, the relative dielectric constant of the material separating the circuit components should be decreased and/or the distance separating the two components should be increased. Since the latter is in contradiction with the trend of further miniaturizing of circuits, the viable solution for decreasing capacitive coupling between adjacent circuit components is to use materials with lower relative dielectric constants to separate the circuit components.
Present dual damascene copper integration schemes typically use silicon dioxide (SiO2) or silicon oxyfluoride (SiOFx) as the inter layer dielectric (ILD) material with an underlying etch stop layer (ESL). In order to reduce the capacitive coupling from line-to-line and layer-to-layer, two broad classes of materials with lower relative dielectric constants are being investigated. The first class of material consists of organic ILD materials such as SILK® or FLARE®. The second class of material consists of carbon doped oxides in which the —Si—O—Si—O— matrix of SiO2 is disrupted with the addition of hydrocarbon groups such as CH3. However, these two classes of materials still have relative dielectric constants ranging from 2.8 to 3.3., which in many cases is still undesirably high.
Some in the relevant art are further reducing the relative dielectric constants of materials by developing porous versions of the low dielectric constant materials. The incorporation of air filled voids lowers the dielectric constant of the material, since air or vacuum are the ultimate low capacitance materials. Using this approach, they have reduced the relative dielectric constant of such porous material to 2.0 to 2.4. However, all of these low dielectric constant materials are structurally inferior to SiO2 and SiOFx, which complicates packaging and assembling the integrated circuit die. An embodiment of the invention includes a method for generating air filled gaps between metal lines, further reducing the line-to-line and layer-to layer capacitive coupling.